1. Field of the Invention
This invention relates to a read/write memory cell in which multiple read only memory data states can be stored.
2. Description of the Related Art
Digital computer systems store information in read only memories (ROM) or read/write memories (R/W). These memories are built in matrix form with multiple rows and columns, the memory cells being located at the intersections of row and column lines. It is known that any of a number of electrical components may be used as a memory cell. For example, one of the earliest ROM memory cells was a resistor selectively connected to the intersections of the row and column lines. The bit status at each bit location was determined by the presence or absence of a particular resistance at the location.
Referring to the branch circuit shown in FIG. 1, the basic principle of operation of a typical ROM memory cell will be disclosed. The memory cell includes a field effect transistor (FET) 10. Data is permanently stored in the memory cell by the selection of particular impedance characteristics of FET 10. For example, the threshold voltage of FET 10 may be determined by ion implantation during the manufacturing process. The drain of FET 10 is connected to a drain potential V.sub.DD. The gate of FET 10 is connected to V.sub.in, which determines if FET 10 is on or off. The source of FET 10 is connected to V.sub.out. When FET 10 is on, V.sub.out will be V.sub.DD minus the threshold voltage of FET 10. The threshold voltage of FET 10 can then be determined by sensing V.sub.out.
If the circuit of FIG. 1 is repeated in array fashion, a ROM memory is formed wherein each of the FET devices functions as a memory cell. The FET gates are connected to word lines and the sources are connected to bit lines. A particular memory cell is read by raising the appropriate word line potential to switch on the FET and sensing the voltage on the appropriate bit line.
R/W memory cells capable of also operating as ROM memory cells are also known. These memory cells include a pair of the branch circuits shown in FIG. 1. The transistors are cross-coupled to act as a flip-flop. At power-up of the device a built in bias, caused by the different DC impedance of each transistor, pulls the flip-flop into a particular data state. The ROM mode of operation is based on sensing the output voltage of either branch circuit immediately following power up, as previously described. Because of the flip-flop structure, the impedances of the two branch circuits are interdependent. If one branch circuit impedance is high, the other must be low, and vice-versa. Only two ROM bits or data states, 0 or 1, are possible depending upon the relative magnitudes of impedance. Thus, only one ROM data state is capable of being stored. The R/W mode of operation is based on controlling the state of the flip-flop after power-up. These R/W memory cells are therefore capable of storing only one ROM data bit and one R/W data bit simultaneously.
As the memory requirements for digital computer systems become more demanding, the storage density of these systems must increase to keep the system from growing prohibitively large and costly. Increasing the ROM data storage capability of previously single bit R/W, single bit ROM memory cells would be one such way of increasing storage density. A R/W memory which is capable of storing multiple ROM data states has heretofore not been recognized.
Personalization is the programming of fixed data into ROM memory cells. Depending on the manufacturing process involved, personalization may occur during the early or late stages of device fabrication. It is advantageous to delay memory personalization until the latter stages of the manufacturing process to allow for late changes in the fixed program to be incorporated into the memory. The ability to personalize a memory cell late in the manufacturing process is known as "late programming capability."
In view of the foregoing, it is desirable to create a R/W memory cell which can store multiple ROM data states. It would also be desirable that such a memory cell have late programming capability.